View AL1402_219753.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TM
General Description
The AL1402 OptoRec interface is designed to decode the ADATa optical data stream and produce four stereo pairs of audio data. Alesis ADATa U.S. patent number 5,297,181. Use of this product requires a license agreement between manufacturer and Alesis Studio Electronics. Details and agreement information are available upon request from Alesis Semiconductor or Alesis Studio Electronics.
Features
Compatible with ADATa Type I and II formats 4 stereo pairs as outputs using standard ADC formats 4 user bit outputs to receive time-code, MIDI data, etc. Internal PLL generates required clocks from optical data. Word Clock input to synchronize outputs to user's system.
Applications
Receive information compatible devices. from ADATa
GND MODE0 FMT0 FMT1 MODE1 OPDIGIN SVCO WDCLK BCLK OUT 1/2 OUT 3/4 OUT 5/6
Figure A. 24 pin SOIC
DS1402-0702
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
eerf elpoep evitaerc tes taht strap eht ekam eW
G G G G G G
VDD LINMODE MUTE ERROR HOLDERR OPDIGTHRU DVCO USER3 USER2 USER1 USER0 OUT 7/8
Table 1
VDD IDD Master IDD Slave GND Fs Temp VIH VIL IIH IIL CIN VOH VOL IOH IOL VOH VOL IOH IOL
Electrical Characteristics and Operating Conditions
Typ
5.0 7.7 5.4 0.0 48 25 5 -
Symbol Description Min Recommended Operating Conditions
Supply Voltage Supply Current, Master Supply Current, Slave Ground Sample rate Temperature Logical "1" input voltage Logical "0" input voltage Logical "1" input current Logical "0" input current Logic Input Capacitance Logical Logical Logical Logical "1" "0" "1" "0" output output output output voltage voltage current current 4.5 30 0 0.75 VDD 0.9 VDD 0.9 VDD -
Max
5.5 55 70 0.25 VDD 1 1 0.1 VDD -8 8 0.1 VDD -2 2
Units
V mA mA V kHz C VDD VDD uA uA pF VDD VDD mA mA VDD VDD mA mA
Inputs (WDCLK, FMT, OPDIGIN, MODE, LINMODE, MUTE, HOLDERR)
Outputs (WDCLK, DVCO, OPDIGTHRU, SVCO, BCLK, ERROR)
Outputs (OUT, USER)
Logical "1" output voltage Logical "0" output voltage Logical "1" output current Logical "0" output current
Table 2
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions
Name
GND MODE0 FMT0 FMT1 MODE1 OPDIGIN SVCO WDCLK BCLK OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8 USER0 USER1 USER2 USER3 DVCO OPDIGTHRU HOLDERR ERROR MUTE LINMODE VDD
Pin Type
Power Input Input Input Input Input Output I/O Output Output Output Output Output Output Output Output Output Output Output Input Output Input Input Power
Description
Ground pin Mode select Format select Format select Mode select Input from optical receiver Derived clock from WDCLK in slave mode; derived from DVCO in Master mode (nominal 12.288MHz, 256x Fs) Input or output word clock, see Table 4, Modes (nominal 48KHz, Fs) Bit clock (nominal 3.072MHz, 64 x Fs) Channels 1 and 2 data output Channels 3 and 4 data output Channels 5 and 6 data output Channels 7 and 8 data output USER0 data bit output. Used to receive timecode USER1 data bit output. Used to receive MIDI data. USER2 data bit output. Reserved. USER3 data bit output. Reserved. Recovered clock from data stream(nominal 12.288MHz, 256 x Fs) OPDIGIN is regenerated and clocked out on this pin to allow daisy-chaining If high, the ERROR pin stays high until the cause of the error is removed AND the HOLDERR pin goes low. Indicates lack of input or failure to synchronize to data stream, mutes data outputs but not clock outputs If high, mutes outputs Tie high +5V power pin
DS1402-0702
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -2-
Master and Slave Modes
Master Mode: All outputs are derived from the input optical format data stream on the OPDIGIN (pin 6). WDCLK is an output. Slave Mode: DAC outputs, USER outputs, BCLK and SVCO outputs are synchronized to WDCLK, which is an input. In Slave mode, WDCLK may be at an arbitrary phase with respect to the incoming samples of OPDIGIN, but if the frequencies aren't identical samples will be dropped, repeated, or garbled. Generally, identical frequencies are achieved by either: using DVCO (pin 18) as the source from which WDCLK is generated, or creating OPDIGIN from a source synchronized to WDCLK.
Use
The AL1402 OptoRec interface has been designed for ease of use and flexibility in systems designed to interface to the ADATa protocol. It supports both left and right justified data formats for ease of integration into existing devices as well as new devices. These formats allow it to operate in parallel with many standard ADC's. The designer uses the FMT0, FMT1, MODE0 and MODE1 pins to select the desired format and mode. The format pins are summarized in Table 3, Formats. The AL1402 provides support for both the ADATa Type I format (16-bit) and the ADATa Type II format (20-bit). Data output is 24 bit. Data input lengths up to 24 bits is supported. USER0 is used to receive the ADATa format 32-bit timcode; USER1 is used to receive MIDI data (if the source device supports these features). USER2 and USER3 are reserved and should not be used.
Table 3 Formats
FMT1
0 0 1 1
FMT0
0 1 0 1
Format
OUT data is right justified, BCLK falls on changing WDCLK OUT data is left justified, BCLK rises on changing WDCLK Chip Reset Gated BLCK, BCLK rises on changing WDCLK
Table 4 Modes
MODE1
0 0 1 1
MODE0
0 1 0 1
Mode
Master mode, WDCLK is an output Slave mode, WDCLK is an input. WDCLK MUST be derived from the same clock supplying the source Reserved Reserved
DS1402-0702
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -3-
TIMING
WDCLK
LEFT CHANNEL
tDU
USER OUT Figure B/Table 5 Output Delay
Symbol Min Typ Max Units -10 2 nsec 27 tDU(Master) -7 5 nsec 30 tDU(Slave) -10 0 nsec 25 tDS(Master) -8 2 nsec 27 tDS(Slave) (Above specifications hold after 3900 WDCLK cycles of valid input at OPDIGIN) VALID
tDS
one period WordClock
WDCLK Left Just 24 ADAT Type II ADAT Type I BCLK (rising) Right Just 24 ADAT Type I
23
MSB
0 0 0
23
MSB
0 0 0
19
MSB
19
MSB
BCLK (falling) Left Just 24 Gated BCLK
23
MSB
WDCLK SVCO
1 1 2 2 3 3 4 4 5 5 124 125 126 127 128 129 130 131 132 133 124 125 126 127 128 129 130 131 132 133 252 253 254 255 256 252 253 254 255 256
Figure C. Output Timing Diagram
DVCO
DS1402-0702
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -4-
a a
ADAT Type II
a a
15
MSB
15
MSB
23
MSB
0 0 0
23
MSB
0 0 0
19
MSB
19
MSB
15
MSB
15
MSB
0
23
MSB
0
Master Mode
Slave Mode
In Slave mode DVCO is not phase aligned with WDCLK and SVCO. MSB bit is sign extended to left of frame. These diagrams represent how data would be framed from an ADAT type I or type II device. They are not actual modes of the AL1402. The Left Justified Mode is recommended for ADAT formats.
Mechanical Specification
Table 6 Package Dimensions Dimensions (Typical) Inches Millimeters
A
24
13
C
B
1 12
7 nom
A .606" 15.40 B .295" 7.50 C .406" 10.30 D .100" 2.50 E .008" 0.20 F .025" 0.64 G .050" 1.27 H .017" 0.42 J .011" 0.27 K .352" 8.94 L .033" 0.83 Notes: 1) Dimension "A" does not include mold flash, protrusions or gate burrs.
K 4 nom
D E G F H
J
L
Figure D. Mechanical Drawing
DS1402-0702
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -5-
Sample Application Schematic
+5V
0.1uF 5 NC INPUT VCC C_LIMIT GND NC
+5V
4 3 2 1 8.2k
OPTOGEN
19 4 5 6 20 VDD OPDGOUT WDCLK RESET WDCLKNEG USER0 USER1 USER2 USER3 FMT0 FMT1 FMT2 FMT3 IN 1/2 IN 3/4 IN 5/6 IN 7/8
0.1uF 11 12 13 14 IN IN IN IN 1/2 3/4 5/6 7/8 TIME CODE 15 16 17 18 7 8 9 10 MIDI DATA +5V
TOTX173* 6 OPTICAL OUT
WDCLK RESET
+5V
5 OUTPUT VCC GND1 GND2 1 3 2 4
47uH
+5V
NC 2 NC 3
NC NC
GND 1
+5V 0.1uF 0.1uF
TORX173*
6
OPTOREC
6 3 4 OPDIGIN FMT0 FMT1 24 VDD OPDIGTHRU OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8 19 10 11 12 13 OPDIGTHRU OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8
OPTICAL IN
ERROR
21 20 ERROR HOLDERR 23 2 5 22 LINMODE MODE0 MODE1 MUTE GND 1
USER0 USER1 USER2 USER3 DVCO SVCO WDCLK BCLK
14 15 16 17 18 7 8 9
TIME CODE NC NC MIDI DATA
DVCO SVCO (Master Mode, can be MCLK)
WDCLK (Slave Mode) WDCLK (Master Mode)
BCLK (Master Mode)
* Optical I/O parts shown are Toshiba parts. The Sharp GP1F33RT or equivalent is also compatible.
LEFTIN RIGHTIN INL/R WDCLK BCLK MCLK OUTL/R WDCLK BCLK MCLK
LEFTOUT RIGHTOUT
ADC
DAC
Figure E. OptoGen/OptoRec setup
The OptoGen accepts input from an ADC, then outputs the Alesis optical format. The OptoRec accepts input in Alesis optical format, then outputs to a DAC.
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -6-
DS1402-0702
Application Notes
The clock and data outputs of the AL1402 are undefined after power-up until a proper data stream is well established at OPDIGIN (pin 6). The clock outputs may be running at an uncontrolled frequency. In this case, the ERROR pin will be high, indicating that the outputs are invalid. This may be prevented by applying logic one to FORMAT1 (pin 4) and logic zero to FORMAT0 (pin 3) on power-up. This resets the AL1402, stopping the VCO clocks and muting the data output. The FORMAT pins may then be set to the value required in your system. Nevertheless the AL1402 will synchronize and produce proper outputs when proper and valid inputs are provided, whether this reset procedure is used or not. The AL1402 in Master Mode can also produce clock outputs running at uncontrolled frequencies if the digital input becomes unstable after stable use, due mostly to poor connection of the optical cable to the optical connector. If this is unwanted in the system an external AND implementation can be used to correct this. The inverted error pin and the desired AL1402 output clock are inputs to the AND and the desired mutable clock is output. This AND function will mute the selected AL1402 clock when the error pin is high (i.e. when unstable input is present at OpDigIn). Care should be taken when running the AL1402 with the AL1201 DAC as the AL1201 DAC will output noise if the AL1402 WDCLK is at an uncontrolled VCO frequency that is beyond the AL1201 maximum frequency. The aforementioned AND function can be used to select the AL1402 WDCLK to be muted when invalid OpDigInput is present before proceeding as the AL1201 WDCLK. See Figure F. with the AND function implemented with NAND gates. In place of this circuit the ERROR pin can be used as a mute select for any audio output stage muting circuitry that may be present in the system.
Figure F. AL1402 -AL1201 CLK MUTE CIRCUIT.
DS1402-0702
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -7-
NOTICE
Alesis Semiconductor reserves the right to make changes to their products or to discontinue any product or service without notice. All products are sold subject to terms and conditions of sale supplied at the time of order acknowledgement. Alesis Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Information contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, no responsibility is assumed for inaccuracies. Alesis Semiconductor products are not designed for use in any applications which involve potential risks of death, personal injury, or severe property or environmental damage or life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. All trademarks and registered trademarks are property of their respective owners.
Contact Information: Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone: (310) 301-0780 Fax: (310) 306-1551 Email: sales@alesis-semi.com
Copyright 2002 Alesis Semiconductor Datasheet July 2002 Reproduction, in part or in whole, without the prior written consent of Alesis Semiconductor is prohibited.
DS1402-0702
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -8-

▲Up To Search▲

Price & Availability of AL1402

	To Download AL1402 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .